A typical storage system on a chip (SOC) device has many functional blocks, e.g., a read channel (RC) block, a hard disk controller (HDC) block; a processor block; and static random access memory block (SRAM). For testing the various blocks, the SOC may be programmed into various “personality” modes. When the SOC is programmed into a personality mode, the definition of digital pins change and the SOC behaves like a discrete device depending on the selected personality mode. In an RC-only mode, the definition of most of the digital pins is changed to pins defined for the RC interface (e.g., the Advanced Technology Attachment (ATA) pins for the normal mode are used as the RC non-return-to-zero (NRZ) pins). This is achieved by multiplexing the block level interface pins out to the SOC pins. While this technique may work for high pin count SOCs (e.g., parallel Advanced Technology Attachment (PATA) SOCs), it may present difficulties with respect to low pin count SOCs.
Current trends see the SOC pin count, and the driving capability of the pins themselves, reducing. For an enterprise class SOC, the RC inside can easily run at 2.5 gigahertz (GHz) (and faster for the future) and, therefore, the SOC pins need to be able to drive the complementary metal oxide semiconductor (CMOS) signals at approximately 250 megahertz (MHz). In low pin count SOCs, the interface pins are not capable of driving more than 50 MHz digital signals. Also, to provide for ten bits of NRZ data, at least twelve pins are needed, not counting the control interface. It is impractical for the low pin count SOC to spare so many pins.